The present invention relates to a method of forming a flash memory device and, more particularly, to a method of forming a flash memory device, which is capable of forming floating gates.
A flash memory device includes a floating gate for storing data and a control gate for transferring voltages.
More specifically, a flash memory device is formed by stacking a tunnel dielectric layer, a floating gate, a dielectric layer, and a control gate over a semiconductor substrate. When a program voltage is applied to the control gate, the coupling ratio between the floating gate and the control gate increases, and electrons are tunneled from the semiconductor substrate to the inside of the floating gate. Accordingly, the threshold voltage rises, so a program operation is performed.
In particular, electrons stored in the floating gate are concentrated more on a surface than in the inside of the floating gate. It is advantageous to increase the area of the floating gate in order to prohibit a shift in the distribution of threshold voltages.
Meanwhile, as the level of integration increases, it becomes difficult to align floating gates on an active area. Accordingly, after forming a conductive layer for the floating gates is formed over a semiconductor substrate, trenches for isolation may be formed by performing an etching process using an isolation mask pattern so that the floating gates are automatically aligned. This is called as a Self-Aligned Floating Gate (SAFG) method.
Further, even in the SAFG method, in order to increase the volumes of floating gates, after a first conductive layer and an isolation layer are formed, a second conductive layer for the floating gates are further formed over the first conductive layer. More specifically, a tunnel dielectric layer and a first conductive layer for floating gates are formed over a semiconductor substrate. An isolation mask pattern is formed on the first conductive layer. An etching process is performed using the isolation mask pattern, thus forming trenches for isolation. In view of the etching process, a width at the bottom of the isolation mask pattern is narrower than that at the top thereof, thus forming a negative profile. Next, after an isolation layer is formed within the trenches, the isolation mask pattern is removed in order to expose the first conductive layer. Next, a second conductive layer for floating gates is formed over the first conductive layer. Since a width at the top of a region from which the isolation mask pattern has been removed is narrower than that at the bottom thereof, over-hang is likely to happen when forming the second conductive layer. Accordingly, void or seam may be generated within the second conductive layer. If void or seam is generated within the floating gates, the electrical characteristics of the flash memory device may be deteriorated, resulting in low reliability.